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cy7c1399bn 256-kbit (32 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-06490 rev. *f revised october 16, 2014 256-kbit (32 k 8) static ram features temperature ranges ? industrial: ?40 c to 85 c ? commercial: 0 c to 70 c ? automotive-a: ?40 c to 85 c single 3.3 v power supply ideal for low-voltage cache memory applications high speed: 12 ns low active power ? 180 mw (max) low-power alpha immune 6t cell available in pb-free and non pb-free plastic soj and tsop- i packages functional description the cy7c1399bn is a high-performance 3.3 v cmos static ram organized as 32,768 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ) and active low output enable (oe ) and tristate drivers. the device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. an active low write enable signal (we ) controls the writing/reading operation of the memory. when ce and we inputs are both low, data on the eight data input/output pins (i/o 0 through i/o 7 ) is written into the memory location addressed by the address present on the address pins (a 0 through a 14 ). reading the device is accomplished by selecting the device and enabling the outputs, ce and oe active low, while we remains inactive or high. under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. the input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (we ) is high. the cy7c1399bn is available in 28-pin standard 300-mil-wide soj and tsop type i packages. g a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 ce i/o 1 i/o 2 i/o 3 32k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 9 a 0 a 11 a 13 a 12 a 14 a 10 logic block diagram
cy7c1399bn document number: 001-06490 rev. *f page 2 of 16 contents pin configurations ........................................................... 3 selection guide ................................................................ 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 5 data retention waveform ................................................ 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 11 ordering code definitions ......................................... 11 package diagrams .......................................................... 12 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc? solutions ...................................................... 16 cypress developer community ................................. 16 technical support ................. .................................... 16
cy7c1399bn document number: 001-06490 rev. *f page 3 of 16 pin configurations figure 1. 28-pin tsop pinout (top view) figure 2. 28-pin soj pinout (top view) 22 23 24 25 26 27 28 1 2 5 10 11 15 14 13 12 16 19 18 17 top view tsop 3 4 20 21 7 6 8 9 oe a 1 a 2 a 3 a 4 we v cc a 5 a 6 a 7 a 8 a 9 a 0 ce i/o 7 i/o 6 i/o 5 gnd i/o 2 i/o 1 i/o 4 i/o 0 a 14 a 10 a 11 a 13 a 12 i/o 3 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view soj 12 13 25 28 27 26 gnd a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 we v cc a 4 a 3 a 2 a 1 i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 5 i/o 0 i/o 1 i/o 2 ce oe a 0 i/o 3 selection guide description condition -12 -15 maximum access time (ns) 12 15 maximum operating current (ma) 55 50 maximum cmos standby current ( ? a) commercial 500 ? commercial (l) 50 ? industrial 500 500 automotive-a ? 500
cy7c1399bn document number: 001-06490 rev. *f page 4 of 16 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [1] ................................?0.5 v to +4.6 v dc voltage applied to outputs in high z state [1] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [1] ............................. ?0.5 v to v cc + 0.5 v output current into outputs (low) ............................. 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ >2001 v latch-up current ....... .............. ........... ............ ........ >200 ma operating range range ambient temperature v cc commercial 0 ? ? c to +70 ? ? c 3.3 v ?? 300 mv industrial ?40 ? ? c to +85 ? ? c automotive-a ?40 ? ? c to +85 ? ? c electrical characteristics over the operating range parameter [1] description test conditions -12 -15 unit min max min max v oh output high voltage min v cc , i oh = ?2.0 ma 2.4 ? 2.4 ? v v ol output low voltage min v cc , i ol = 4.0 ma ? 0.4 ? 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il [1] input low voltage ?0.3 0.8 ?0.3 0.8 v i ix input leakage current ?1 +1 ?1 +1 ? a i oz output leakage current gnd ? v in ? v cc , output disabled ?5 +5 ?5 +5 ? a i cc v cc operating supply current max v cc , i out = 0 ma, f = f max = 1/t rc ?55?50ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce ? v ih , v in ? v ih , or v in ? v il , f = f max commercial?5??ma commercial (l)?4??ma industrial ?5?5ma automotive-a???5ma i sb2 automatic ce power-down current ? cmos inputs [2] max v cc , ce ? v cc ? 0.3 v, v in ? v cc ? 0.3 v, or v in ? 0.3 v, we ? v cc ? 0.3 v or we ?? 0.3 v, f=f max commercial ? 500 ? ? ? a commercial (l) ? 50 ? ? ? a industrial ? 500 ? 500 ? a automotive-a ? ? ? 500 ? a notes 1. minimum voltage is equal to ? 2.0 v for pulse durations of less than 20 ns. 2. device draws low standby current regardless of switching on the addresses.
cy7c1399bn document number: 001-06490 rev. *f page 5 of 16 capacitance parameter [3] description test conditions max unit c in : addresses input capacitance t a = 25 ?? c, f = 1 mhz, v cc = 3.3 v 5 pf c in : controls 6pf c out output capacitance 6pf ac test loads and waveforms figure 3. ac test loads and waveforms [4] 3.0 v 3.3 v output r1 317 ?? r2 351 ?? c l including jig and scope gnd 90% 10% 90% 10% ? 3ns ? 3 ns output 1.73 v equivalent to: thvenin equivalent all input pulses 167 ?? data retention characteristics (over the operating range - l version only) parameter description conditions min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v 020 ? a t cdr chip deselect to data retention time 0?ns t r operation recovery time t rc ?ns data retention waveform figure 4. data retention waveform 3.0 v 3.0 v t cdr v dr ? 2 v data retention mode t r ce v cc notes 3. tested initially and after any design or proce ss changes that may affect these parameters. 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and capacitance c l = 30 pf.
cy7c1399bn document number: 001-06490 rev. *f page 6 of 16 switching characteristics over the operating range parameter [5] description -12 -15 unit min max min max read cycle t rc read cycle time 12 ? 15 ? ns t aa address to data valid ? 12 ? 15 ns t oha data hold from address change 3 ? 3? ns t ace ce low to data valid ? 12 ? 15 ns t doe oe low to data valid ? 5 ? 6 ns t lzoe oe low to low z [6] 0? 0? ns t hzoe oe high to high z [6, 7] ?5? 6 ns t lzce ce low to low z [6] 3? 3? ns t hzce ce high to high z [6, 7] ?6? 7 ns t pu ce low to power-up 0 ? 0? ns t pd ce high to power-down ? 12 ? 15 ns write cycle [8, 9] t wc write cycle time 12 ? 15 ? ns t sce ce low to write end 8 ? 10 ? ns t aw address setup to write end 8 ? 10 ? ns t ha address hold from write end 0 ? 0? ns t sa address setup to write start 0 ? 0? ns t pwe we pulse width 8 ? 10 ? ns t sd data setup to write end 7 ? 8? ns t hd data hold from write end 0 ? 0? ns t hzwe we low to high z [8] ?7? 7 ns t lzwe we high to low z [6] 3? 3? ns notes 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and capacitance c l = 30 pf. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzce , t hzwe are specified with c l = 5 pf as in ac test loads. transition is measured 500 mv from steady state voltage. 8. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing shoul d be referenced to the rising edge of the signal that termina tes the write. 9. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1399bn document number: 001-06490 rev. *f page 7 of 16 switching waveforms figure 5. read cycle no. 1 [10, 11] figure 6. read cycle no. 2 [11, 12] address data i/o previous data valid data out valid t rc t aa t oha 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu data i/o high impedance impedance icc isb t hzoe t hzce t pd oe ce high v cc supply current notes 10. device is continuously selected. oe , ce = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low.
cy7c1399bn document number: 001-06490 rev. *f page 8 of 16 figure 7. write cycle no. 1 (we controlled) [13, 14, 15] figure 8. write cycle no. 2 (ce controlled) [13, 14, 15] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note 16 t wc t aw t sa t ha t hd t sd t sce we data i/o address ce data in valid notes 13. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing shou ld be referenced to the rising edge of the signal that termina tes the write. 14. data i/o is high impedance if oe = v ih . 15. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 16. during this period, the i/os are in the output state and input signals should not be applied.
cy7c1399bn document number: 001-06490 rev. *f page 9 of 16 figure 9. write cycle no. 3 (we controlled, oe low) [17, 18] switching waveforms (continued) data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce we t hzwe note 19 data in valid notes 17. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 18. the minimum write cycle pulse width should be equal to the sum of t hzwe and t sd . 19. during this period, the i/os are in the output state and input signals should not be applied.
cy7c1399bn document number: 001-06490 rev. *f page 10 of 16 truth table ce we oe input/output mode power h x x high z deselect/power-down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high z deselect, output disabled active (i cc )
cy7c1399bn document number: 001-06490 rev. *f page 11 of 16 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurations and features. the following table contai ns only the list of parts that are currently available. for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products or contact your loca l sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturer's representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . speed (ns) ordering code package diagram package type operating range 12 cy7c1399bn-12vxc 51-85031 28-pin molded soj (pb-free) commercial CY7C1399BN-12ZXC 51-85071 28-pin tsop i (pb-free) cy7c1399bnl-12zxc 28-pin tsop i (pb-free) cy7c1399bn-12vxi 51-85031 28-pin molded soj (pb-free) industrial 15 cy7c1399bn-15zxi 51-85071 28-pin tsop i (pb-free) industrial cy7c1399bn-15vxa 51-85031 28-pin molded soj (pb-free) automotive-a contact your local sales representative regarding availability of these parts. temperature range: x = c or i or a c = commercial i = industrial a = automotive-a x = pb-free package type: x = v or z v = 28-pin molded soj z = 28-pin tsop i speed: xx = 12 ns or 15 ns l = low power process technology: bn = 0.25 m 399 = 256-kb density with data width 8 bits family code: 1 = fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress cy 1 - c x xx 7399 c x l bn
cy7c1399bn document number: 001-06490 rev. *f page 12 of 16 package diagrams figure 10. 28-pin soj (300 mils) v28.3 (mo lded soj v21) package outline, 51-85031 51-85031 *e
cy7c1399bn document number: 001-06490 rev. *f page 13 of 16 figure 11. 28-pin tsop i (8 13.4 1.2 mm) z28 (standard) package outline, 51-85071 package diagrams (continued) 51-85071 *j
cy7c1399bn document number: 001-06490 rev. *f page 14 of 16 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mv millivolt mw milliwatt ns nanosecond pf picofarad vvolt wwatt
cy7c1399bn document number: 001-06490 rev. *f page 15 of 16 document history page document title: cy7c1399bn, 256-kbit (32 k 8) static ram document number: 001-06490 revision ecn orig. of change submission date description of change ** 423877 nxr see ecn new data sheet. *a 498575 nxr see ecn added automotive-a range. removed i os parameter from dc electrical characteristics table. updated ordering information table. *b 2896382 aju 03/19/2010 removed obsolete part numbers from ordering information table. updated package diagrams. *c 3053362 pras 10/08/2010 removed pruned part numbers cy7c1399bnl-15vxc and cy7c1399bnl-15vxct. added ordering code definitions. *d 3383869 tava 09/26/2011 added commercial temperatur e range under features section on page 1. removed reference to an1064-sram system design guidelines on page 1. modified the notes in figures under read cycle and write cycle sections. rearranged sections for better clarity. revised package diagrams. added acronyms and units of measure. updated template according to current cypress standards. *e 4121360 vini 09/12/2013 updated in new template. completing sunset review. *f 4540416 vini 10/16/2014 updated switching waveforms : updated note 18. updated package diagrams : spec 51-85071 ? changed revision from *i to *j. completing sunset review.
document number: 001-06490 rev. *f revised october 16, 2014 page 16 of 16 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1399bn ? cypress semiconductor corporation, 2006-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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